![]() The apparatus as claimed in claim 6, wherein the M bit-pair data are read from M different memory blocks of the FIFO memory, respectively.ĩ. The apparatus as claimed in claim 6, wherein the frequency of the read clock signal is substantially T times of the frequency of the write clock signal, wherein the number T is a half of a bit amount of the image data of the pixel divided by M.Ĩ. ![]() The apparatus as claimed in claim 1, wherein the controller writes image data of a pixel into the FIFO memory within one clock cycle of a write clock signal.ħ. The apparatus as claimed in claim 1, wherein the apparatus is integrated within a timing controller.Ħ. The apparatus as claimed in claim 3, wherein the first order read pointer is for pointing to an address of one of the plurality of memory blocks, and the second order read pointer is for pointing to an address of one of the plurality of memory units.ĥ. ![]() The apparatus as claimed in claim 1, wherein the controller reads the stored image data out of the FIFO memory according to a first order read pointer and a second order read pointer.Ĥ. The apparatus as claimed in claim 1, wherein the controller writes the image data into the FIFO memory according to a write pointer.ģ. An apparatus for accessing a plurality of image data, comprising: a FIFO memory for storing the image data, wherein the image data comprises a plurality of pixel data corresponding to a plurality of pixels respectively, the FIFO memory comprises a plurality of memory blocks, and each of the memory blocks comprises a plurality of memory units and a controller for accessing the FIFO memory in circular manner wherein the controller writes each of the pixel data of the image data into N memory blocks of the FIFO memory on a pixel-basis and reads the stored image data in channel-basis, and the stored image data are respectively read out to a plurality of output channels in a read clock cycle, and within one clock cycle of a read clock signal, the controller reads M bit-pair data of the stored image data from M memory blocks of the plurality of memory blocks of the FIFO memory to M output channels, respectively the numbers N and M being positive integers greater than 1.Ģ. ![]()
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